1. Field of the Invention
The present invention relates to the samplers used for measuring characteristics of high speed signals, such as used with transient digitizers and high speed oscilloscopes.
2. Description of Related Art
A conventional oscilloscope displays a waveform in step with an external event, or in "real time". The trace of the waveform sweeps across the screen in a matter of nanoseconds or picoseconds, for example, and then quickly fades. For a human observer to see the trace, repeated sweeps are usually needed to make the trace appear with an observable, steady brightness. Thus, a repetitive input signal is required. Transient digitizers circumvent the need for a repeated input by electrically recording the transient event in real time for later readout or viewing at a much slower rate, in what is known as "equivalent time".
There are two basic types of transient digitizers on the commercial market, one based on CRT technology and the other based on a continuously running Analog-to-Digital Converter (ADC). The fastest of the two are the CRT-based digitizers, and they are based on a dual electron-beam approach. One beam operates in real time and writes a trace onto a screen containing a charge-storing diode array. The diode array captures the charge deposited by the "writing" beam and that charge is later read-out by a "read" beam at a slow, equivalent-time rate. The disadvantage to the CRT approach lies in the expensive and bulky CRT, and ultimately, in its limited bandwidth. Two companies of which Applicant is aware offer a CRT-based digitizer, an 80 picosecond rise-time unit by Tektronix and a 50 picosecond unit by Intertechnique of France.
The continuously running Analog-to-Digital Converter (ADC) electrically samples the signal and very rapidly converts the sample to a digital number for real-time storage in digital memory. A limitation of the ADC digitizer is that it must perform complicated operations in real-time, i.e., convert signals to binary data and store the result in a large digital memory array before the next sample is taken. The fastest ADC-based digitizer is about 10 times slower than a CRT digitizer and requires a large amount of power and cooling. Nevertheless, these relatively low bandwidth ADC devices have been at the focus of the electronics marketplace since they are the core technology of a recent oscilloscope development, the Digital Storage Oscilloscope (DSO). DSOs can function as transient digitizers at speeds running 10-1000 times slower than CRT-based digitizers.
Other prior art digitizers are based on a periodically-tapped transmission line, with a sample and hold circuit located at each tap. See, U.S. Pat. No. 4,825,103, entitled SAMPLE AND HOLD CIRCUIT, invented by Hornak; Sedlmeyer, et al., "ANALYZER FOR FAST SINGLE EVENTS", reprinted from "NUCLEAR ELECTRONICS III" by the International Atomic Energy Agency Vienna, 1962; Schwarte, "Sampling System for Recording Fast Single Events", ELECTRONICS LETTERS, Vol. 8, No. 4, Feb. 24, 1972; Riad, "Modeling of the HP-1430A Feedthrough Wideband (25-ps) Sampling Head", IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, Vol. IM-31, No. 2, June, 1982, pp. 110-115.
The tapped-transmission line architecture is attractive for a number of reasons. First, the sample and hold circuits located at each tap can operate at speeds well above that of the competing technologies. Experimental single samplers have been operated at 1.3 ps risetime. Rodwell, et al., "GaAs Nonlinear Transmission Lines for Picosecond Pulse Generation and Millimeter Wave Sampling", IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, Vol. 39, No. 7, July, 1991, pp. 1194-1204. In contrast, CRT technology is believed to be limited to about 50 ps.
Demultiplexers have been used to increase the effective input sample rate of digitizers. A demultiplexer performs the inverse operation of a multiplexer by accepting sequential signals from a single input, and through a commutating action, distributing samples of the input to multiple outputs.
A key feature of a demultiplexer is that it provides a substantially reduced sample rate to each of the outputs of the demultiplexer relative to the effective input sample rate. For instance, if there are 100 outputs and the input sample rate is 10 gigasamples/sec (GS/s), the output sample rate is reduced by a factor of 100 to 0.1 GS/s. Essentially, the demultiplexer provides a means to slow data rates by performing a serial-to-parallel conversion.
If a sample and hold (S/H) circuit is located at each output, a sampling demultiplexer is formed. Thus, rapidly changing input signals can be distributed to multiple S/H outputs, where each output sample is held steady by the S/H for subsequent processing, such as analog-to-digital (A/D) conversion at a rate slower than the effective sampling rate by a factor of the number of samplers.
The state-of-the-art in ND conversion is 0.5 GS/s, achieved through the use of one or more monolithic ND chips. For faster conversion rates, a sampling demultiplexer is used to drive multiple A/D converters.
The state-of-the-art in sampling demultiplexers is based on high-speed integrated circuits operating at about 4 GS/s. Integrated circuit demultiplexers are limited in several ways: 1) the analog bandwidth of the input circuitry is generally limited to 1 GHz by transistor performance limitations, and 2) the sample rate is limited by the accuracy of the interleave timing, i.e., the ability to accurately locate multiple transistorized sampling circuits in time.
Accordingly, it is desirable to provide a tapped transmission line architecture which provides a robust and simple design for practical applications. Furthermore, it is desirable to provide a high speed sampler which relies on fewer components, enabling widespread applications of high speed samplers, including for instance more economical digitizers for high sample count applications and pulse compressors.